The present invention relates to phase-lock frequency synthesizers and more particularly relates to single-loop synthesizers.
Frequency synthesizers are known. They are used especially in radiocommunications as a source of the radiofrequency signal in the transmission circuitry and as a local transposition oscillator in the reception circuitry. In frequency-hopping radiocommunications systems where the frequency is changed according to a certain rate and a certain relationship, the rate of change of frequency, quantified in terms of number of hops per second, is limited by the reverse of the time taken by the synthesizer to go from one frequency to another frequency. The need for ever faster synthesizers has led to the making of multiple-loop synthesizers, for example synthesizers with three loops: a main loop that generates a first signal whose frequency may vary in steps of, for example, 1 MHz or more, a secondary loop with an output divider that generates a second signal whose frequency and steps of variation can be adjusted independently of those of the first signal and are, for example, about fifty times smaller because of the division by the output divider and an addition loop that takes the sum of the first signal and the second signal. The drawback of these multiple-loop synthesizers is that they call for a far greater number of variable oscillators. Thus, for a three-loop oscillator, it is necessary to have nine different oscillators to cover two octaves because one and the same oscillator cannot cover more than half an octave but in the secondary loop it is possible, instead of changing the oscillator, to change the division ratio of the output divider. Now, variable oscillators consume current, take up space, are costly and entail the risk of causing parasitic signals in the synthesizer if they are not sufficiently decoupled with respect to one another.